Exclusive

Publication

Byline

Location

US Patent Issued to Micron Technology on April 7 for "Methods used in forming a memory array comprising strings of memory cells including insulator walls in a through-array-via region" (Idaho Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,972, issued on April 7, was assigned to Micron Technology Inc. (Boise, Idaho). "Methods used in forming a memory array comprising strings o... Read More


US Patent Issued to Micron Technology on April 7 for "Microelectronic devices, and related memory devices, electronic systems, and methods" (Idaho Inventor)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,973, issued on April 7, was assigned to Micron Technology Inc. (Boise, Idaho). "Microelectronic devices, and related memory devices, electr... Read More


US Patent Issued to XINTEC on April 7 for "Chip package and manufacturing method thereof" (Taiwanese Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,974, issued on April 7, was assigned to XINTEC INC. (Taoyuan City, Taiwan). "Chip package and manufacturing method thereof" was invented by... Read More


US Patent Issued to SAMSUNG ELECTRONICS on April 7 for "Integrated circuit device" (South Korean Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,975, issued on April 7, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Integrated circuit device" was invented by J... Read More


US Patent Issued to SAMSUNG ELECTRONICS on April 7 for "Semiconductor device" (South Korean Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,976, issued on April 7, was assigned to SAMSUNG ELECTRONICS Co. Ltd. (Gyeonggi-do, South Korea). "Semiconductor device" was invented by Jeo... Read More


US Patent Issued to Intel on April 7 for "Fill of vias in single and dual damascene structures using self-assembled monolayer" (Oregon Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,977, issued on April 7, was assigned to Intel Corp. (Santa Clara, Calif.). "Fill of vias in single and dual damascene structures using self... Read More


US Patent Issued to SAMSUNG ELECTRONICS on April 7 for "Semiconductor device having a source/drain contact connected to a back-side power rail by a landing pad and a through electrode" (South Korean Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,978, issued on April 7, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Semiconductor device having a source/drain c... Read More


US Patent Issued to Apple on April 7 for "Dual contact and power rail for high performance standard cells" (California Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,979, issued on April 7, was assigned to Apple Inc. (Cupertino, Calif.). "Dual contact and power rail for high performance standard cells" w... Read More


US Patent Issued to International Business Machines on April 7 for "Front end of line processing compatible thermally stable buried power rails" (New York Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,980, issued on April 7, was assigned to International Business Machines Corp. (Armonk, N.Y.). "Front end of line processing compatible ther... Read More


US Patent Issued to QUALCOMM on April 7 for "Port landing-free low-skew signal distribution with backside metallization and buried rail" (Belgian, American Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,598,981, issued on April 7, was assigned to QUALCOMM Inc. (San Diego). "Port landing-free low-skew signal distribution with backside metallizat... Read More